Since DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) performs the input/output of data at twice the frequency of the external clock using both the rising and falling edges of the clock, the valid data window is narrower than that of SDR SDRAM (Single Data Rate Synchronous Dynamic Random Access Memory). In DDR SDRAM, a bi-directional data strobe signal DQS is used because the controller side notifies the timing of the data transfer from the DRAM to the receiver and the DRAM notifies the timing of the data transfer from the controller to the receiver. In other words, the data strobe signal DQS is used as an operation reference clock for data input/output during read/write operations.
During a read operation, the edges of the data strobe signal DQS from the DDR SDRAM and read data DQ coincide (the edges of clock signals CK and /CK approximately coincide with them as well) as shown in FIG. 3 because of a DLL (Delay Lock Loop) circuit and internal control within the DDR SDRAM. Therefore, the interface (the controller), not shown in the drawing, performs sampling upon delaying the data strobe signal DQS until the center of the read data DQ using a phase shift circuit disposed in the controller when the interface receives the read data DQ and the data strobe signal DQS from the DDR SDRAM (refer to Patent Document 1). Further, in FIG. 3, the phase between the edges of the data strobe signal DQS against one cycle (360 degrees) of the clock signals CK and /CK is 180 degrees, and the interface circuit (the controller) phase shifts the data strobe signal DQS by 90 degrees and samples the read data DQ during a read operation.
Further, during a write operation, the rising and falling edges of the DQS supplied by the interface (the controller) side, not shown in the drawing, to the DDR SDRAM are placed in the center of write data DQ as shown in FIG. 3. The DQS is supplied to DDR SDRAM with its phase delayed by 90 degrees in relation to that of the DQ as shown in FIG. 3. The receiver of the DDR SDRAM fetches data based on the rising and falling transitions of the DQS as references.
The circuit structure of the output and input sides of the data DQ and the data strobe signal DQS in the conventional DDR SDRAM interface is schematically shown in FIG. 4. Referring to FIG. 4, on the output side, a phase shift circuit 20′ outputs the data DQ with its phase shifted by 90 degrees in relation to that of the clock signal CLK (a synchronous signal supplied to the interface and the DDR SDRAM) and outputs the data strobe signal DQS with its phase shifted by 180 degrees in relation to that of the same clock signal CLK. Latch circuits 12 and 13 latch the DQ and the DQS, respectively, using the clock from the phase shift circuit 20′ and output to output terminals via output buffers 14 and 15, respectively. By doing this, the setup/hold time of the receiver of the DDR SDRAM, not shown in the drawing, can be obtained.
The read data DQ and the data strobe signal DQS are outputted from the DDR SDRAM at the same timing on the input side, and input buffers 16 and 17 receive the read data DQ and the data strobe signal DQS outputted from the DDR SDRAM, respectively. A phase shift circuit 30′ outputs the data strobe signal DQS with its phase shifted by 90 degrees and a sampling circuit 40 samples the read data DQ from the input buffer 16 based on the data strobe signal outputted from the phase shift circuit 30′ with its phase shifted by 90 degrees (refer to Patent Document 1). By doing this, the setup/hold time of the sampling circuit 40 can be obtained.
For instance, when testing the output function (the circuit system that shifts the phases of the write data and the data strobe signal DQS by 90 degrees and 180 degrees and output them to the DDR SDRAM) of the interface shown in FIG. 4, an output signal is compared to an expected value using a tester (ATE: Automatic Test Equipment). Further, when testing the input/output function (the circuit system that receives the read data and the data strobe signal DQS from the DDR SDRAM, shifts the phase of the data strobe signal DQS by 90 degrees, and samples the read data) of the interface, a signal is fed by the tester to see whether or not it operates normally.
Further, the interface is applied to, for instance, AMB (Advanced Memory Buffer) on DIMM such as FB-DIMM (Fully Buffered Dual Inline Memory Module). The AMB sends/receives data to/from the DRAM on the DIMM, buffers the data internally on the chip, and sends/receives the data to/from the AMB on the subsequent DIMM or the memory controller using point-to-point communication.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2005-78547A